1. Technical Field
The present invention relates generally to the data processing field and, more particularly, to layouts of ternary and binary content addressable memory cells for a data processing system.
2. Description of the Related Art
Content addressable memory (CAM) is a specialized type of memory. Unlike random access memory (RAM), where one uses a given address to randomly access the data stored there, CAM has the capability to supply an address, based on the value stored at or associated with the address. Additionally, an array of CAM cells will have built-in comparison circuitry for every cell of hardware memory. This allows a massively parallel search, where every bit in memory is searched simultaneously. Consequently, the hardware can provide an extremely fast search of a large set of information.
This makes CAMs suitable for applications where fast searches are required, such as imaging, voice recognition, and networking applications. In networking applications, for instance, CAMs are used to control the traffic of packets on the Internet and make sure that the proper information arrives at its destination as specified in the header (e.g. an URL or email address). In many network systems, stand-alone CAM products are used, which then interface, for example, with an application specific integrated circuit (ASIC) to provide the proper function. However, in order to reduce system cost, power consumption and improve performance, there is a desire to embed CAM functionality within an ASIC as a system-on-chip solution. Therefore, there is a strong need to develop high-density, high-performance CAM bitcells. Present layouts do not meet this need, for reasons that will be discussed.
Short Lesson in CAM Circuitry
CAMs are typically derived from a high-density 6T-SRAM (static random-access memory) bitcell, so an understanding of the circuitry of a bitcell can aid in understanding the complexities of a CAM array. FIG. 1 discloses a circuit diagram of a 6T-SRAM bitcell 100. The bitcell 100 consists of two PMOS (positive-channel metal-oxide semiconductor) transistors P1, P2, four NMOS (negative-channel metal-oxide semiconductor) transistors N1, N2, N3, N4, two bitlines BL, /BL for signal detection, one wordline WL used for reading and writing data to the cell, and the power supplies Vdd, Vss. Bitlines BL, /BL (read as bar BL) carry complementary values, i.e., one is high and one is low, when the cell is written. After writing, the cell will contain a single bit of information, e.g., if it was written with BL=low, /BL=high, the cell will have a value of zero while if it was written with BL=high, /BL=low, the cell will have a value of one. The data is stored through two, cross-coupled inverters, with this configuration allowing the information to be maintained without the need for constantly refreshing, as is the case in DRAM (dynamic random-access memory). Although other bitcell circuits have been proposed and used, the 6T-SRAM cell shown is the one most commonly used in the industry for memory, especially for high-density applications.
Two types of CAM bitcells can be formed from this 6T SRAM bitcell: binary and ternary, which will be explained along with their structures. FIG. 2 discloses a binary CAM (BCAM) bitcell 200. BCAM bitcell 200 will not only store the bit of information in the SRAM structure above, here denoted 202, but also contains two complementary hitlines HBL, /HBL that provide the data for comparison, comparison circuit 204, composed of four additional NMOS transistors N5, N6, N7, N8 that compare the cell data to the hitlines HBL, /HBL, and a matchline ML that indicates if there is a match or not. Because the bitcell, like the SRAM cell above, can have a value of only zero or one, a comparison between the value carried in the bitcell and the value carried in the hitlines can only result in two answers: match or no-match.
More recently, ternary CAM (TCAM) bitcells have been developed that can provide an additional option, a “Don't care” value. To add this extra possible choice, a TCAM bitcell contains two 6T-SRAM portions and their respective programming circuits, although no additional hitlines are added. FIG. 3 discloses a TCAM bitcell 300. Bitcell 300 contains two 6T-SRAM bitcells 302A, 302B, but only one comparison circuit 304 and associated hitlines HBL, /HBL. Table 1 below shows the possible values for BCAM cells, while Table 2 shows possible values for TCAM cells.
TABLE 1BCAMBL/BLCell Value010101
TABLE 2TCAMBL1/BL1BL2/BL2Cell Value010100110Don't care1001Not used10101As discussed previously, a binary CAM has only two values and will either match or not match against the hitlines. In the ternary CAM, there are four possible combinations of values shown by the bitline, although one of the possible values, with both BL1 and /BL2 high, is not used. When both BL1 and /BL2 are low, this signals a “don't care” value, which will show as a match against any value. This allows some portions of a pattern to be ignored while other portions are compared.
Problems Encountered in Designing CAM Layouts
Due to the increasing use of large CAM memories in System-on-Chip (SoC), it is necessary that a high density of such memories be achieved while still delivering the highest possible performance. The proper design of unit binary or ternary CAM bitcells is, therefore, of great importance in order to optimize chip density and performance.
In addition, with the advent of more advanced process technologies, such as the 90 nanometer (nm) process, the yield and performance of CAMs are much more sensitive to process-layout interactions as compared to previous technologies. For example, it is known that mechanical stresses that are induced in shallow trench isolation (STI) directly impact the performance of transistors due to the transfer of these stresses to the metal-oxide semiconductor (MOS) channel region. The negative effect of stress on transistor performance is directly dependent on the distance between the STI edge and the transistor. SRAM cells, owing to tighter design rules, are generally more affected by such process-layout interactions. In order to be used in advanced process technologies such as the 90-nm process, the layouts of binary and ternary CAM cells need to be such that these process-layout interaction effects are minimized
Also, advanced process technologies, such as the 90-nm process, offer more choices for threshold voltages (Vt) of transistors compared to older technologies. For 6T SRAM cells, a high NMOS and PMOS Vt is typically chosen to achieve a high static noise margin (SNM); and, at the same time, to achieve low leakage and adequate write-margins. For example, a low NMOS Vt within a cell will lower the SNM of the cell creating problems with reliable storage of the memory bit (to offset this a higher beta ratio must be used, increasing the cell size). On the other hand, a low PMOS Vt within a 6T cell will lower the write margin, while somewhat increasing the SNM. Keeping these factors in mind, it is a generally accepted practice to maintain the Vt in the devices within a 6T cell high. However, within a CAM cell, the transistors responsible for the match operation do not directly influence the storage stability or the read/write performance of the memory cell. These transistors can therefore have their threshold voltages set separately from the 6T-SRAM transistors in order to deliver desired performance and leakage targets. It is desirable that the layout of the CAM cell will allow this separate threshold voltage setting.
Prior Art Solutions
In order to use similar layouts for both binary and ternary CAM cells, current implementations generally make use of a symmetric 6T-SRAM-layout architecture. This allows comparison circuit 204 to be easily connected to either a single 6T-SRAM bitcell to create a binary CAM or to two 6T-SRAM bitcells to make a ternary CAM. FIGS. 4A and 4B show a prior art layout for 6T-SRAM bitcell 100 and for half of a comparison circuit, such as the right half of circuit 204. FIG. 4A shows the symmetric active areas and polysilicon lines for the 6T SRAM 402 and the comparison circuit 404, which is connected to the true internal node. FIG. 4B shows the metal-1 and metal-2 layers for the same device layouts. In FIG. 4A, 6T-SRAM cell 402 is composed of P-type diffusion regions 406, N-type diffusion regions 408, 412, and polysilicon gate lines 420, 422, and 424. N-type diffusion region 412 is used for the NWELL connection. Furthermore, comparison circuit 404 contains N-type diffusion regions 410 and polysilicon gate lines 426 and 428. Contacts 430-458 from the gates and/or diffusion areas to metal 1 are also shown. FIG. 4B discloses the metal-1 layer, which includes segments 480-494 and the metal-2 layer, which includes segments 470-478; it additionally repeats contacts 430-458 to help provide reference between the two drawings. Here, metal 1 segment 480 is used for Vdd power connection and segment 486 is used for Vss connection. Furthermore, metal 1 segment 482 represents internal node 208 and segment 484 represents node 206 of the 6T-SRAM cell. Metal 2 segments 470 and 471 represent the bitlines of the 6T-SRAM cell, while segment 476 represents one of the hitlines of comparison circuit 304 in FIG. 3. Comparing FIG. 4A to the circuit of FIG. 3, gate lines 420, 422 form the gates for transistors P1B, N2B, P2B, N4B, and gate line 424 forms the gates for transistors N1B and N3B. Contacts 438, 440 provide the nodes by which these segments are connected to the internal nodes of the 6T-SRAM cell. Contact 454 connects transistor gates N1B and N3B to the wordline. Contact 452 connects to bitline 470 (BL or BL2), while contact 456 connects to the associated (complementary) bitline 471 (/BL or /BL2). Contact 430 provides a connection to Vdd, which is carried in metal-1 segment 480, while contacts 444, 448 make the connection to Vss metal-1 segment 486. Metal-1 segment 482 ties contacts 432, 440, 442 together to form one of the internal nodes, while segment 420 similarly ties contacts 434, 438, 446 together in another internal node. Within comparison circuit 404, contact 448 is connected to Vss, carried in metal-2 474, and 450 carries matchline ML. Gate lines for transistors N7 and N8 or for N7B and N8B are carried by segment 426, which is connected through contact 458 to /HBL 476, and by gate line 428.
We have discussed how the assembly of building blocks for 6-T SRAM bitcell 402 and comparison circuit 404 forms ternary CAM sub-blocks 302B. Comparing schematics of binary CAM 200 of FIG. 2 with ternary CAM 300 of FIG. 3, it becomes clear to those skilled in the art that each individual portion 302A or 302B can form a binary cell 200 by either adding transistors N7A and N8A to portion 302A, or transistors N5B and N6B to portion 302B. Hence, assembly of building blocks 402 and 404 can be used to make either a binary CAM array or a ternary CAM array, as will be shown in the following figures. Showing only the substrate level and gate lines, FIG. 5A discloses two BCAM bitcells as they would be laid out for an array. Each BCAM bitcell 500 contains one 6-T SRAM bitcell 502 and two comparison circuits 504. FIG. 5B discloses the same layouts used to form two TCAM bitcells as laid out for an array. Here, each TCAM bitcell 500′ contains two 6-T SRAM bitcells 502 and two comparison circuits 504.
Among shortcomings of the CAM cell layout illustrated in FIGS. 4A,B and FIGS. 5A, B include the following:                a) Difflision region 408 can be seen in FIG. 4A to form an inverted “U”. In an array, this shape is mirrored into the cell below, while the bitline contact is shared between the cells forming a “donut-shaped” diffusion region. The rectangular region that is enclosed by the diffusion regions contains silicon dioxide for isolation. The structure of an isolation region completely surrounded by a diffusion region leads to stress-related effects that can significantly impact the performance and/or yield of the memory cell. As such, it is typically required that in SRAM cells that have this feature, the enclosed areas must have an area equal or grater than a given value, which can increase the size of the cell.        b) The proximity between diffusion area 408, which forms the n-type transistors for the SRAM bitcell, and diffusion area 410, which forms the n-type transistors for the comparison circuit, is sufficiently small that it is difficult to have different implants in these two areas. Because of this, it is difficult to set the threshold voltages Vt of these devices separately to optimize their different uses.        c) The patterns for polysilicon and for contact/metal 1 are relatively difficult to implement while still achieving a compact cell size. Design rules, such as metal-1 spacing, as well as metal-1 overlap of contacts, determine overall cell size. These rules must be aggressively approached with this conventional device. Because the width of the polysilicon lines in FIG. 4A vary along the length of the line, this design is inherently less conducive to achieving the SPICE modeling targets. The design also results in larger polysilicon end-caps being required.        d) Area-wise, the layout illustrated in FIGS. 4A and 4B results in a larger cell area than is desired.        
It should be emphasized that most of the shortcomings listed above become increasingly more important with more advanced technology processes such as the 90 nm process. Therefore, it is important to have “process-friendly” CAM cell layouts that specifically address issues posed by process-layout interactions; and, at the same time, that deliver aggressive memory area densities.
U.S. Pat. No. 6,522,563 describes a method for achieving a more compact CAM cell layout. However, the described approach changes the design of the CAM cell at the transistor level by using p-channel transistors as access transistors to the SRAM cells to improve the efficiency of layout of the cell array. The use of p-channel transistors as access transistors greatly reduces the performance of the SRAM cell (for a given size of transistor used) because PMOS devices inherently have lower channel mobility than NMOS devices.
There is, accordingly, a need for an improved layout of binary and ternary CAM cells that achieves a more compact cell layout without altering the transistor schematics of the CAM cells, and that is “process friendly” to accommodate requirements of advanced process technologies such as the 90 nm process.